What is a latch（Latch-up）？

The parasitic thyristor (SCR) structure in CMOS technology is formed by interconnecting the parasitic NPN/PNP transistors of NMOS and PMOS. These parasitic transistors are normally turned off, but when subjected to voltage spikes, static interference or high temperatures, they trigger a positive feedback loop, causing the current to be amplified indefinitely inside the chip, eventually burning the chip or forcing the system to power down. This phenomenon is known as the latching effect.

CMOS structure (left) and its equivalent circuit (right)

How to quickly determine if a circuit has a latch?

The latch may be a problem if you encounter the following:

Sudden surge of current: the chip power consumption surges, far beyond the normal working current.

l voltage sudden plunge: the power supply voltage "cliff drop", resulting in chip reset or dysfunction.

High temperature is more likely to collapse: the chip is more likely to trigger the latch in a high temperature environment (such as >85℃).

Detection method:

l Electrostatic test: simulate human contact discharge to verify the anti-ESD capability of the chip (IEC 61000-4-2).

l Surge test: Simulate lightning strikes or power fluctuations to test circuit stability (IEC 61000-4-5).

Computer simulation: Use simulation tools (such as TCAD) to predict the trigger threshold of parasitic structures and optimize the design.

"Trigger threshold" and protection scheme of different devices：

Leiditech Electronics "anti-latch Arsenal"

1. High power interface: TVS diode + self-restoring fuse

TVS diode: nanosecond response, clamping voltage spikes to a safe threshold to prevent parasitic transistors from triggering.

Self-restoring fuse (PPTC) : automatically disconnect the circuit when overcurrent, and automatically reset after troubleshooting to avoid continuous damage. Together, they can block the latch trigger condition.

2. Low voltage/high speed interface: ESD ESD protection

Low-capacitance ESD devices: like an "anti-static jacket", wrap the chip interface to prevent electrostatic "shock" from triggering the latch, while not affecting the signal speed (such as USB, HDMI).

Leiditech recommended "anti-latch weapons" list, choose according to the scene, simple and effective, detailed program can pay attention to Lei MAO electronic public number or contact Leiditech EMC brother

类型	型号	描述	封装	应用
ESD	ULC0524BLC	5V,0.3/0.8PF,5A	DFN2510P10	DP接口静电防护
ESD	SDA1211CDN	12V,Bi,8PF,8A	DFN1006	12V电源接口防静电
ESD	SD24C	24V,Bi,50PF,12A	SOD-323	CAN接口静电防护
ESD	SMC24	24V,Bi,30PF,9A	SOT-23	CAN接口静电防护
ESD	ESDA05CP	5V Bi, 10PF,5A	DFN1006-2	GPIO静电保护
ESD	SDA05W5	5V,Uni,30PF,3A	SOT-353	GPIO静电保护
ESD	ULC332010T8	3.3V,1.5PF,30A	DFN2010-8	千兆网防静电
ESD	GBLC03C	3.3V,Bi,0.6 PF,20A	SOD-323	千兆网防静电
ESD	SLVU2.8-4	2.8V,Bi,2 PF,30A	SOP-08	千兆网防静电
ESD	USRV05-4	5V,Uni,0.7PF,5A	SOT-26	SD卡静电防护
ESD	ULC3304P10	3.3V,Uni, 0.4PF,5A	DFN2510P10	HDMI 2.0静电保护
ESD	SR05W	5V,Uni,3PF,20A	SOT-143	USB2.0 静电保护
ESD	LC0502D6	5V,0.8PF,6A	SOT-26	USB2.0静电防护
ESD	ULC05DT3	5V,Uni,0.6PF,4A	SOT-23	eSATA静电保护
ESD	ULC0568K	5V,0.3PF,5A	DFN4120-10	USB3.0静电保护
ESD	ULC0502P3	5V,Uni,0.6PF,5A	DFN1006-3	USB3.0 静电保护
ESD	ULC0524P	5V,Uni,0.3PF,5A	DFN2510P10	USB3.0静电保护
ESD	SMC12	12V,Bi,45PF,15A	SOT-23	I2C接口静电保护
ESD	ULC0504P	5V,0.4PF,5A	DFN1616-6	TF卡静电保护
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